Jackson Lecture 2 VHDL design example continued PROCESS ( resetn, clk ) ELSE BEGIN y IF resetn THEN END y WHEN C ELSIF AND THEN IF THEN CASE y IS y WHEN A ELSE IF THEN y y END ELSE END y END END END PROCESS WHEN B z WHEN ELSE IF THEN END y Electrical Computer Engineering Dr. Jackson Lecture Representing states A SIGNAL is defined, of the State_type, to represent the outputs TYPE State_type IS (A, B, SIGNAL y: The signal, y, can be used to represent the outputs for an FSM that has three states Electrical Computer Engineering Dr. Jackson Lecture 1 User defined data types The TYPE keyword will be used to define a new data type used to represent states in the FSM TYPE State_type IS (A, B, A data type definition Data type name Valid values for the data type Defines a data type (called State_type) that can take on three distinct values: A, B, or C). Jackson Lecture FSM design using CAD tools VHDL provides a number of constructs for designing finite state machines There is not a standard way for defining an FSM Basic approach Create a data type to represent the possible states of an FSM This signal represents the outputs (state variables) of the that implement the states in the FSM VHDL compiler chooses the appropriate number of during the synthesis process The state assignment can be done the compiler or can be user specified Electrical Computer Engineering Dr. Preview text ECE380 Digital Logic Design of Finite State Machines Using CAD Tools Electrical Computer Engineering Dr.

Finite state machine design